Studies on Design for Delay Testability and Delay Test Generation for Sequential Circuits

VLSI (Very Large Scale Integration) circuits are basic components of today’s complex digital systems. In order to realize dependable digital systems, VLSI circuits should be highly reliable. VLSI testing plays an important role in satisfying this requirement. VLSI testing is to check whether faults exist in a circuit, and it consists of two main phases: test generation and test application. In test generation, a test sequence that is an input sequence to detect faults in a circuit is generated. In test application, the generated test sequence is applied to the circuit. Conventional testing deals with stuck-at faults only. For today’s high-speed VLSI circuits, testing for stuck-at faults is not sufficient to guarantee the timing correctness of the circuits. Delay testing that is to check whether delay faults exist in a circuit is an important technology to guarantee the timing correctness. For delay faults in a combinational circuit, two-pattern tests are required to detect them. On the other hand, for delay faults in a sequential circuit, we need a test sequence whose length is two or more. Test generation for sequential circuits under simple fault models such as the single stuck-at fault model is generally a hard task. Delay test generation for sequential circuits is a more challenging problem. For such sequential circuits, design for testability (DFT) is an important approach to reduce the test generation complexity. Fully enhanced scan design has been proposed as a straightforward DFT method for delay faults. In this design, every flip-flop (FF) is replaced by an enhanced scan FF (ESFF). ∗Doctor’s Thesis, Department of Information Processing, Graduate School of Information Science, Nara Institute of Science and Technology, NAIST-IS-DT0261007, July 28, 2004.